{"id":295,"date":"2020-12-11T10:17:26","date_gmt":"2020-12-11T09:17:26","guid":{"rendered":"http:\/\/blog.zhaw.ch\/high-performance\/?p=295"},"modified":"2020-12-11T10:24:48","modified_gmt":"2020-12-11T09:24:48","slug":"secure-boot-concept-for-the-zynq-ultrascale-mpsoc","status":"publish","type":"post","link":"https:\/\/blog.zhaw.ch\/high-performance\/2020\/12\/11\/secure-boot-concept-for-the-zynq-ultrascale-mpsoc\/","title":{"rendered":"Secure Boot Concept for the Zynq Ultrascale+ MPSoC"},"content":{"rendered":"\n<p>The complexity of today&#8217;s multiprocessor System-on-Chip (MPSoC) can lead to major security risks in embedded designs, as the available security functions are often not or insufficiently utilized.<\/p>\n\n\n\n<p>InES (Institute of Embedded Systems at ZHAW) developed a reference design which demonstrates a concept of a secure boot implementation and runtime system on a Xilinx Zynq Ultrascale+.<\/p>\n\n\n\n<p>The security concept includes dedicated on-chip security features like AES, RSA and hashing core. The reference design also describes how to implement a voltage and temperature tamper detection. In addition, secure key storage and various methods to minimize key usage are provided. The demonstrator implements the ARM Trust Zone technology with OP-TEE as a secure operating system. <\/p>\n\n\n\n<p>Implementation examples and usage description of the Linux Crypto-API, using the dedicated cryptographic cores, are also included in the documentation.<\/p>\n\n\n\n<p>The modular open-source reference design is provided on GitHub, which contains implementation examples for all the above features.<\/p>\n\n\n\n<p>Please find the link to our secure boot reference design here:<\/p>\n\n\n\n<p><a href=\"https:\/\/github.com\/InES-HPMM\/ZYNQ_USplus_secure_boot_reference_design\">https:\/\/github.com\/InES-HPMM\/ZYNQ_USplus_secure_boot_reference_design<\/a><\/p>\n\n\n\n<p><br><\/p>\n","protected":false},"excerpt":{"rendered":"<p>The complexity of today&#8217;s multiprocessor System-on-Chip (MPSoC) can lead to major security risks in embedded designs, as the available security functions are often not or insufficiently utilized. InES (Institute of Embedded Systems at ZHAW) developed a reference design which demonstrates a concept of a secure boot implementation and runtime system on a Xilinx Zynq Ultrascale+. [&hellip;]<\/p>\n","protected":false},"author":271,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ngg_post_thumbnail":0,"footnotes":""},"categories":[1],"tags":[],"features":[],"class_list":["post-295","post","type-post","status-publish","format-standard","hentry","category-allgemein"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v27.2 (Yoast SEO v27.2) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Secure Boot Concept for the Zynq Ultrascale+ MPSoC - Embedded High Performance Multimedia Blog<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/blog.zhaw.ch\/high-performance\/2020\/12\/11\/secure-boot-concept-for-the-zynq-ultrascale-mpsoc\/\" \/>\n<meta property=\"og:locale\" content=\"en_GB\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Secure Boot Concept for the Zynq Ultrascale+ MPSoC\" \/>\n<meta property=\"og:description\" content=\"The complexity of today&#8217;s multiprocessor System-on-Chip (MPSoC) can lead to major security risks in embedded designs, as the available security functions are often not or insufficiently utilized. InES (Institute of Embedded Systems at ZHAW) developed a reference design which demonstrates a concept of a secure boot implementation and runtime system on a Xilinx Zynq Ultrascale+. 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