{"id":243,"date":"2020-04-27T08:33:32","date_gmt":"2020-04-27T06:33:32","guid":{"rendered":"http:\/\/blog.zhaw.ch\/high-performance\/?p=243"},"modified":"2020-04-27T08:36:30","modified_gmt":"2020-04-27T06:36:30","slug":"znnn-the-framework-to-port-neural-networks-to-fpga","status":"publish","type":"post","link":"https:\/\/blog.zhaw.ch\/high-performance\/2020\/04\/27\/znnn-the-framework-to-port-neural-networks-to-fpga\/","title":{"rendered":"ZNNN the Framework to Port Neural Networks to FPGA"},"content":{"rendered":"\n
BY TOBIAS WELTI AND HANS-JOACHIM GELKE<\/p>\n\n\n\n
Due to their hardware architecture, Field Programmable Gate Arrays (FPGAs) are optimally suited for the execution of machine learning algorithms. These algorithms require the calculation of millions or even billions of multiplications for each input. To successfully accelerate a neural network, parallel execution of multiplication is the key. The obvious suggestion for parallel execution is a Graphics Processing Unit (GPU), offering hundreds of execution cores. For years, GPU vendors have been adapting the capabilities of their GPUs to meet the demand for narrow integer and floating-point data types used in AI. But still, a GPU will execute one Neural Network (NN) layer after the other, with data transfers between computation cores and memory.<\/p>\n\n\n\n
Implementing Neural Networks in FPGAs has several advantages:<\/p>\n\n\n\n
Flexible bit widths for both integer and fixed-point data types.<\/li>
Large numbers of scalable hardware multiplier cores.<\/li>
Flexibility due to tightly coupled memory blocks with wide parallel interfaces, allowing access to vast numbers of data points in each clock cycle.<\/li><\/ol>\n\n\n\n
Considering the previous points, the FPGA clearly provides all the resources required for highly parallel execution of NN algorithms.<\/p>\n\n\n\n
Existing\nframeworks<\/strong><\/p>\n\n\n\n
Unfortunately,\nthe act of porting a trained network to HDL code for implementation in the FPGA\nis not trivial. FPGA vendors have started to provide frameworks for running NNs\nin their devices. These include HDL-coded NN-coprocessor cores as IP blocks and\nmatching compilers to convert a trained NN into a binary executable which will\nrun on the coprocessor. However, these frameworks are based on a specific\nsoftware library and therefore require a processor core running an operating\nsystem and controlling software. This means that the NN input data and network\nparameters are transferred from the software to the coprocessor in order to\ncalculate the output of the NN. The output values are then transferred back to\nthe software for interpretation.<\/p>\n\n\n\n
This is\nsubstantial overhead, especially if the input data is sampled or preprocessed\nin the FPGA fabric. It would be preferable to implement the neural network\nentirely in the FPGA fabric, capable of running independently from software.<\/p>\n\n\n\n
The ZHAW\nNative Neural Network (ZNNN) framework is aimed at the following goals:<\/p>\n\n\n\n
<\/p>\n\n\n\n
Input may be received directly from FPGA fabric<\/li>
Inference independent of CPU and software<\/li>
Minimal latency<\/li>
Maximal throughput<\/li>
No access to DRAM required<\/li><\/ul>\n\n\n\n
With these\ngoals in mind, it is obvious that we trade in flexibility to gain performance\nand simplicity. The NN is implemented as a rigid block, designed for one single\nNN application. To allow for minimum latency, we use dedicated multipliers for\neach neuron, and each layer has its own memory block for the weights and\nbiases. Ping-Pong buffers allow to process one input vector in one layer while\nreceiving the next input vector. With this structure, pipelining delays can be\nminimized to the execution time of the largest layer.<\/p>\n\n\n\n
Our framework will take as input a structured text file with a description of the NN, including number of inputs, data-bit widths, fix point precision, number of neurons per layer for fully connected layers, number of filters and kernel size for convolutional layers, max pool and flatting layers. From this configuration file and a training and verification data set, it will generate:<\/p>\n\n\n\n
Input A trained NN model<\/li>
A behavioural model written in C programming language to generate a data set for verification of the VHDL code in simulation<\/li>
A test bench for verification<\/li>
The VHDL code of the NN ready for instantiation in your design.<\/li><\/ul>\n\n\n\n
<\/figure>\n\n\n\n
Dedicated\nmultipliers for the neurons will use a significant amount of the available\nresources and it must be noted that larger networks will require considerably\nlarger devices. This will not be suitable for all NN applications. Our ZNNN\nframework is optimally suited for applications such as industrial machine\nsurveillance where only small networks will meet the latency requirements while\nstill achieving the required accuracy.<\/p>\n\n\n\n
Performance<\/strong><\/p>\n\n\n\n
A direct\ncomparison of ZNNN with the Deep Learning Processing Unit (DPU) coprocessor\nfrom Xilinx shows that both have their justification, depending on the\napplication at hand:<\/p>\n\n\n\n
If you need\nto run multiple, different neural networks on your FPGA with a fair\nperformance, you should go with the Xilinx solution. The DPU allows to process\ndifferent NN on the same implementation but is restricted to\nsoftware-controlled operation.<\/p>\n\n\n\n
If\nperformance is essential and your application needs a single neural network,\nyou should use the ZNNN.<\/p>\n\n\n\n
The amount\nof resources in a Xilinx Zynq UltraScale+ EG9 device used by the different\nsolutions is shown in the following table. The ‘Xilinx DPU’ will always use\nroughly the same amount of resources (depending on its configuration). It can\nprocess various neural networks, including very large ones, with a trade-off in\nthroughput and processing time (latency). The resource requirements of ZNNN\nstrongly depend on the size and type of NN you implement. ‘ZNNN MNIST’ is a NN\nwith only dense layers, trained for the well-known MNIST example. MNIST is a NN\napplication that recognizes handwritten numbers. ‘ZNNN CONV’ is a NN using\n1D-convolutional layers for non-linear signal processing in an industrial\napplication which accepts 64 data points as input. ‘ZNNN VIS’ is a dense\nnetwork with 2304 inputs and one single output, used for an industrial\napplication. According to the large number of inputs, the number of multipliers\nrequired is very large.<\/p>\n\n\n\n
Throughput of a NN can be measured in the number of inputs processed per second (FPS). On the Xilinx DPU, the whole NN is processed for one set of input data before the next set can be passed. Our ZNNN framework implements layer pipelining, meaning that as soon as the first layer is processed, the next input set can be accepted as shown in the following figure.<\/p>\n\n\n\n<\/figure>\n\n\n\n
The latency\nis slightly increased because not all layers have the same processing time, but\nall the layers are processed in parallel. In return, the delay between two\ninputs is greatly reduced, allowing to process more FPS. Because ZNNN includes\nall the required weight parameters in the design, these don’t need to be loaded\ninto the FPGA at runtime. This allows to increase the FPS by orders of\nmagnitude in comparison with the Xilinx DPU.<\/p>\n\n\n\n
Conclusion<\/strong><\/p>\n\n\n\n
Both the power and the cost of ZNNNs become visible in comparison with the\nDPU: The DPU offers the flexibility to run various NNs on one implementation,\nincluding larger NNs like Resnet50. The DPU is controlled by software and\ntherefore requires a CPU running a Linux operating system. ZNNN implementations\nare ideal for small NNs and run independently from software, take their input\ndirectly from FPGA and process orders of magnitude faster than the DPU!<\/p>\n\n\n\n
The ZNNN\nframework is suitable for low latency, high throughput execution of small\nconvolutional and fully connected NNs. It generates VHDL code for a specific NN\nimplementation in FGPA without the development overhead of hand-written HDL\ncode and testbenches. The processing performance of the ZNNN is orders of\nmagnitude faster than Xilinx’ DPU thanks to a high level of pipelining.<\/p>\n\n\n\n
We are aware that the ZNNN implementation can require more FPGA resources than the DPU, but there are industrial applications where this approach is a perfect fit and the achieved performance meets the requirements. With the ZNNN running independently of CPU and software and the input data coming directly from the FPGA fabric, we have principally no bottlenecks in the design.<\/p>\n\n\n\n
Our team will continually improve the ZNNN framework by making trade-offs between resource requirements and performance configurable.<\/p>\n\n\n\n
BY TOBIAS WELTI AND HANS-JOACHIM GELKE Due to their hardware architecture, Field Programmable Gate Arrays (FPGAs) are optimally suited for the execution of machine learning algorithms. These algorithms require the calculation of millions or even billions of multiplications for each input. To successfully accelerate a neural network, parallel execution of multiplication is the key. The […]<\/p>\n","protected":false},"author":271,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ngg_post_thumbnail":0,"footnotes":""},"categories":[1],"tags":[],"features":[],"class_list":["post-243","post","type-post","status-publish","format-standard","hentry","category-allgemein"],"yoast_head":"\n
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